library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


-- Clock divider
entity clock_div is
	generic (
		Divider : integer := 10
	);
	port (
		CLK_in : in std_logic; 
		CLK_o  : out std_logic;
		CLK_o_n: out std_logic
	);
end clock_div;

architecture rtl of clock_div is
begin
	process (CLK_in)
		variable count : integer := 0;
	begin
		if (rising_edge(CLK_in)) then
			count := count + 1;
			if (count < Divider) then
				CLK_o <= '1';
				CLK_o_n <= '0';
			elsif (count >= Divider) then
				CLK_o <= '0';
				CLK_o_n <= '1';
			end if;
			if (count = 2*Divider) then
				count := 0;
			end if;
		end if;
	end process;
end rtl;